Features: • Organized 1,048,576 x 4• Single +5V ±10% power supply• Enhanced Page-Mode operation for faster memory accessHigher data bandwidth than conventional page-mode partsRandom Single-Bit Access within a row with a column address• CAS\-Before-RAS\ (CBR) Refresh• ...
SMJ44400: Features: • Organized 1,048,576 x 4• Single +5V ±10% power supply• Enhanced Page-Mode operation for faster memory accessHigher data bandwidth than conventional page-mode partsRando...
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The SMJ44400 is a series of 4,194,304-bit dynamic random- access memories (DRAMs), organized as 1,048,576 words of four bits each. This series employs state-of-the-art technology for high performance, reliability, and low-power operation.
The SMJ44400 features maximum row access times of 80ns, 100ns, and 120ns. Maximum power dissipation is as low as 360mW operating and 22mW standby.
All SMJ44400 inputs and outputs, including clocks, are compatible with Series 54 TTL. All addressses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ44400 is offered in a 400-mil, 20-pin ceramic side-brazed dual-in-line package (JD suffix) and a 20-pin
ceramic flatpack (HR suffix) that are characterized for operation from -55°C to +125°C.