SN100KT5573

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Supply voltage range, V_EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 V to 0 V
Input voltage range, T_TL (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.2 V to 7 V
Input voltage range, E_CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..VEE to 0 V
Input current range, T_TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 mA to 5 mA
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
Voltage applied to any output in the disabled or power-off state . . . . . . .0.5 V to 5.5 V
Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . .0.5 V to VCC
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed.

This SN100KT5573 octal ECL-to-TTL translator is designed to provide efficient translation between a 100K ECL signal environment and a TTL signal environment. SN100KT5573 is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory address drivers, clock drivers, and bus oriented receivers and transmitters.

The eight latches of the SN100KT5573 are transparent D-type latches. While latch enable (LE) is low, the Q outputs follow the data (D) inputs. When LE is high, the Q outputs are latched at the levels that were set up at the D inputs.

A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. Output-enable OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.The SN100KT5573 is characterized for operation from 0° to 85° C.