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SN54ABT16500B

Features: Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-BBiCMOS DesignSignificantly Reduces Power Dissipation UBT(Universal Bus Transceiver)Combines D-Type Latches and D-TypeFlip-Flops for Operation in Transparent,Latched, or Clocked ModeESD Protection Exceeds 2000 V PerMIL...

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SeekIC No. : 004496288 Detail

SN54ABT16500B: Features: Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-BBiCMOS DesignSignificantly Reduces Power Dissipation UBT(Universal Bus Transceiver)Combines D-Type Latches and D-Type...

SN54ABT16500B Data Sheet

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Part Number:
SN54ABT16500B
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Members of the Texas Instruments Widebus Family State-of-the-Art  EPIC-BBiCMOS Design
Significantly Reduces Power Dissipation UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,Latched, or Clocked ModeESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP(Output Ground Bounce)
< 0.8 V at VCC= 5 V, TA = 25°C
High-Impedance State During Power Up and Power Down
Flow-Through Architecture Optimizes PCB Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . ... . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO. ..0.5 V to 5.5 V
Current into any output in the low state, IO:SN54ABT16500B . . . . . . . . . . . . . .. . . 96 mA
                                                                      SN74ABT16500B . . . . . . . . . . .  .  . . .128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . ..  . . . . . . . . . .. .. . . 18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .50 mA
Package thermal impedance, JA (see Note 2):DGG package . . . . . . . . . . . . . ..  .  81°C/W
                                                                          DL package . . . . .. . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C


Description

SN54ABT16500B, SN74ABT16500B 18-BIT UNIVERSAL BUS TRANSCEIVERS
These SN54ABT16500B, SN74ABT16500B 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.Data flow in each direction is controlled by output-enable (OEAB and OEBA, latch-enable(LEAB and LEBA), and clock (CLKABandCLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB ishigh.

When LEAB is low, the A data is latched if CLKABis held at a high or low logic level. If LEABs low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. OEAB is active-high. When OEAB is high, the outputs areactive. When OEAB is low, the outputs of SN54ABT16500B, SN74ABT16500B  are in thehigh-impedance state.




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