SN54ABT16543

Features:

 Members of the Texas Instruments WidebusE Family
 State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation
 Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
 Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
 Flow-Through Architecture Optimizes PCB Layout
 High-Drive Outputs (32-mA IOH, 64-mA IOL)
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings



Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..0.5 V to 7 V
Input voltage range, V_I (except I/O ports) (see Note 1)  . . . . . . . . . . . . . . ..0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V_O  . .0.5 V to 5.5 V
Current into any output in the low state, I_O:SN54ABT16543 . . . . . . . . . . . . .         .96 mA
                                                                      SN74ABT16543 . . . . . . . . . . . . . . . .  128 mA
Input clamp current, I_IK (V_I < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   . . .50 mA
Package thermal impedance, q_JA (see Note 2): D_GG package  . . . . . . . . . . .     . . . 81°C/W
                                                                           D_L package  . . . . . . . . . . . . . . . . ..74°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..65°C to 150°C


Description

  The SN54ABT16543 16-bit registered transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. The SN54ABT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA ) and output-enable (OEAB or OEBA ) inputs are provided for each register to permit independent control in either direction of data flow.

   The A-to-B enable (CEAB ) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using theCEBA , LEBA , and OEBA inputs. To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16543 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN54ABT16543 is characterized for operation from 40°C to 85°C.