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SN54ABT16825

Features: ` Members of the Texas Instruments WidebusE Family` State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation` Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17` Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C` High-Impedance Stat...

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SN54ABT16825: Features: ` Members of the Texas Instruments WidebusE Family` State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation` Latch-Up Performance Exceeds 500 mA Per JEDEC Standar...

SN54ABT16825 Data Sheet

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Part Number:
SN54ABT16825
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` Members of the Texas Instruments WidebusE Family
` State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation
` Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
` Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
` High-Impedance State During Power Up and Power Down
` Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
` Flow-Through Architecture Optimizes PCB Layout
` High-Drive Outputs (32-mA IOH, 64-mA IOL)
` Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . .. . 0.5 V to 5.5 V
Current into any output in the low state, IO:SN54ABT16825 . . . . . . . .. . .. . .. . .. . . . . .96 mA
                                                                       SN74ABT16825 . . . . . . .. . .. . .. .. . . . . . .128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . . . . . . . . . . . .18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . .. . ... . . . . . . . . . . . . . . . . . . .50 mA
Package thermal impedance, qJA (see Note 2): DGG package . . . . .. . .. . .. . .. . . . . . .81°C/W
                                                                           DL package . . . . . . . .. . .. . .. . . . . . . .74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C


Description

The SN54ABT16825 are 18-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. SN54ABT16825 can be used as two 9-bit buffers or one 18-bit buffer. They provide true data.

The 3-state control gate of SN54ABT16825 is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all nine affected outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the SN54ABT16825 is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor SN54ABT16825 is determined by the current-sinking capability of the driver.

The SN54ABT16825 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT16825 is characterized for operation from 40°C to 85°C.




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