SN54ABT16952

Features:

Members of the Texas Instruments Widebus^TM Family
 State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
 Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
 Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
 Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
 Flow-Through Architecture Optimizes PCB Layout
 High-Drive Outputs (32-mA I_OH, 64-mA I_OL)
 Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Fla(WD) Package Using 25-mil Center-to-Center Spacings



Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..0.5 V to 7 V
Input voltage range, V_I (except I/O ports) (see Note 1)  . . . . . . . . . . . . . . ..0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V_O  . .0.5 V to 5.5 V
Current into any output in the low state, I_O:SN54ABT16543 . . . . . . . . . . . . .         .96 mA
                                                                      SN74ABT16543 . . . . . . . . . . . . . . . .  128 mA
Input clamp current, I_IK (V_I < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   . . .50 mA
Package thermal impedance, q_JA (see Note 2): D_GG package  . . . . . . . . . . .     . . . 81°C/W
                                                                           D_L package  . . . . . . . . . . . . . . . . ..74°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..65°C to 150°C  


Description

   The SN54ABT16952 are 16-bit registered transceivers that contain two sets of D-type flip-flops for temporary storage of data flowing in either direction. The 'ABT16952 can be used as two 8-bit transceivers or one 16-bit transceiver. Data of SN54ABT16952 on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or  OEBA) input low accesses the data on either port.

   To ensure the high-impedance state during power up or power down, OE of SN54ABT16952 should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

   The SN54ABT16952 is characterized for operation over the full military temperature range of 55°C to 125°C.

   The SN74ABT16952 is characterized for operation from 40°C to 85°C.