SN54ABT18502

• Member of the Texas Instruments SCOPE^TM Family of Testability Products
• Member of the Texas Instruments WidebusE Family
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• UBT E (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Two Boundary-Scan Cells per I/O for Greater Flexibility
• State-of-the-Art EPIC-IIB E BiCMOS Design Significantly Reduces Power Dissipation
• SCOPE E Instruction Set
IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP,and HIGHZ
Parallel-Signature Analysis at Inputs With Masking Option
Pseudo-Random Pattern Generation From Outputs
Sample Inputs/Toggle Outputs
Binary Count From Outputs
Device Identification
Even-Parity Opcodes
• Packaged in 68-Pin Ceramic Quad Flat Package Using 25-mil Center-to-Center Spacings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, V_I (I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Voltage range applied to any output in the high state or power-off state, V_O . . . 0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT18502 . . . . . . . 96 mA
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . .  50 mA
Continuous current through V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 mA
Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 mA
Maximum power dissipation at T_A = 55 (in still air) . . . . . . . . . . .  . 885 mW
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.

The SN54ABT18502 scan test device with 18-bit universal bus transceiver is a member of the Texas Instruments SCOPEE testability integrated circuit family. SN54ABT18502 supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, SN54ABT18502 is an 18-bit universal bus transceiver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry of SN54ABT18502 can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPEE universal bus transceiver.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs of SN54ABT18502 are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPEE SN54ABT18502 universal bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations of SN54ABT18502 are synchronized to the TAP interface.

Additional flexibility SN54ABT18502 is provided in the test mode through the use of two boundary-scan cells (BSCs) for each I/O pin. SN54ABT18502 allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.

The SN54ABT18502 is characterized for operation over the full military temperature range of 55 to 125.