SN54ABT18646

The SN54ABT18646 scan test device with 18-bit bus transceivers and registers is a member of the Texas Instruments SCOPEE testability integrated circuit family. SN54ABT18646 supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, the SN54ABT18646 is an 18-bit bus transceiver and register that allows for multiplexed transmission of data directly from the input bus or from the internal registers. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry of SN54ABT18646 can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode SN54ABT18646 does not affect the functional operation of the SCOPEE bus transceivers and registers.
Transceiver function of SN54ABT18646 is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When OE is high, both the A and B outputs of SN54ABT18646 are in the high-impedance state, effectively isolating both buses.

Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB and SAB, respectively. Figure 1 illustrates the four fundamental bus-management functions, SN54ABT18646 can be performed with the SN54ABT18646.

In the test mode, the normal operation of the SCOPEE SN54ABT18646 bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry of SN54ABT18646 can perform boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins of SN54ABT18646 observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions of SN54ABT18646 such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Additional flexibility of SN54ABT18646 is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction also SN54ABT18646 is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.

The SN54ABT18646 is characterized over the full military temperature range of 55°C to 125°C.