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Features: State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power DissipationTwo 8-Bit Back-to-Back Registers Store Data Flowing in Both DirectionsNoninverting OutputsTypical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°CLatch-Up Performance Exceeds 500 mA Per JESD 17E...

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SeekIC No. : 004496327 Detail

SN54ABT2952A: Features: State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power DissipationTwo 8-Bit Back-to-Back Registers Store Data Flowing in Both DirectionsNoninverting OutputsTypical VOLP (Ou...

SN54ABT2952A Data Sheet

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Part Number:: SN54ABT2952A
Supply Ability:: 5000

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Upload time: 2025/12/24

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Product Details

Description

Features:

State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions
Noninverting Outputs
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs

Pinout

Connection Diagram

Specifications

Supply voltage range, V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I(except I/O ports) (see Note 1) . . . . . . . . . . . .. . . . . . . . . . . . .0.5 V to 7 V
Voltage applied to any output in the high state or power-off state, V_O . . . . . . . . . .0.5 V to 5.5 V
Current into any output in the low state, I_O: SN54ABT2952 . . . . . . . . . . . . .. . . . . . . . . . . .. . .96 mA
                                                                       SN74ABT2952A . . . . . . . . . . . . . . . .. . . . . . .. .128 mA
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Package thermal impedance, _JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . .104°C/W
                                                                          DW package . . . .. . . . . . . . . . . . . . . . . . .. .81°C/W
                                                                          NT package . . . .. . . . . . . . . . . . . . . . . . . . . . 67°C/W
                                                                          PW package . . . . . . . . . . . . . . . . . . . . . . .. .120°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .    . . .. . . .65°C to 150°C

Description

The SN54ABT2952A transceivers consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.

To ensure the high-impedance state of SN54ABT2952A during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT2952A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT2952A is characterized for operation from 40°C to 85°C.

SN54ABT2952A

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