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SN54ABT32543

Features: • Members of the Texas Instruments Widebus+TM Family• State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, T...

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SeekIC No. : 004496332 Detail

SN54ABT32543: Features: • Members of the Texas Instruments Widebus+TM Family• State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation• Latch-Up Performance Exceeds 500...

SN54ABT32543 Data Sheet

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Part Number:
SN54ABT32543
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

• Members of the Texas Instruments Widebus+TM Family
• State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
• Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
• High-Drive Outputs (32-mA IOH, 64-mA IOL)
• Bus-Hold Inputs Eliminate the Need for External Pullup Resistors
• Packaged in 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 * 14-mm Body Using 0.5-mm Lead Pitch  


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7V 
Voltage range applied to any output in the high state or power-off state, VO  . . . . . .0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT32543  . . . . . . . . . . . . . . . . .  . . . . . . . .96 mA
                                                                       SN74ABT32543  . . . . . . . . . . . . . . . . . . .  . . . . .128 mA
Input clamp current, IIK (VI < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 mA
Output clamp current, IOK (VO < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   . . . . . . . .50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2)  . . . . . . . . . .. . . . . . . . . . . . .1.2 W
Storage temperature range  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .65°C to 150°C 


Description

The 4ABT32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. SN54ABT32543 can be used as two 18-bit transceivers or one 36-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs of SN54ABT32543 are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB) input of SN54ABT32543 must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor SN54ABT32543 is determined by the current-sinking capability of the driver.

Active bus-hold circuitry of SN54ABT32543 is provided to hold unused or floating data inputs at a valid logic level.

The SN54ABT32543 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT32543 is characterized for operation from 40°C to 85°C.




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