Features: Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
Two Independent 64 * 36 Clocked FIFOs Buffering Data in Opposite Directions
Mailbox-Bypass Register for Each FIFO
Dynamic Port-B Bus Sizing of 36 Bits (Long Word), 18 Bits (Word), and 9 Bits (Byte)
Selection of Big- or Little-Endian Format for Word and Byte Bus Sizes
Three Modes of Byte-Order Swapping on Port B
Almost-Full and Almost-Empty Flags
Microprocessor Interface Control Logic
EFA, FFA, AEA, and AFA Flags Synchronized by CLKA
EFB, FFB, AEB, and AFB Flags Synchronized by CLKB
Passive Parity Checking on Each Port
Parity Generation Can Be Selected for Each Port
Low-Power Advanced BiCMOS Technology
Supports Clock Frequencies up to 50 MHz
Fast Access Times of 12 ns
Released as DSCC SMD (Standard Microcircuit Drawing) 5962-9560901QYA and 5962-9560901NXD
Package Options Include 132-Pin Ceramic Quad Flat (HFP) and 120-Pin Plastic Quad Flat (PCB) Packages
Pinout
SpecificationsSupply voltage range, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . .. . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC ) . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC ) . . . . . . . . . . . . . . . . . .. . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
DescriptionThe SN54ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. SN54ABT3614 supports clock frequencies up to 50 MHz and has read-access times as fast as 12 ns. Two independent 64 * 36 dual-port SRAM FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. FIFO SN54ABT3614 data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register SN54ABT3614 has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port.
The SN54ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The SN54ABT3614 enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface.
The full flag and almost-full flag of a FIFO SN54ABT3614 are two-stage synchronized to the port clock that writes data to it sarray. The empty flag and
ost-empty flag of a FIFO are two-stage synchronized to the port clock that reads data from its array.
The SN54ABT3614 is characterized for operation over the full military temperature range of 55 to 125.
SN54ABT3614 Data Sheet
