Features: Output Ports Have Equivalent 25-W Series Resistors, So No External Resistors Are Required
State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25 °C
Typical VOLV (Output Undershoot) < 0.5 V at VCC = 5 V, TA = 25° C
Package Options Include Plastic Small-Outline (DW) Package and Ceramic Chip Carriers (FK) and DIPs (JT)
Pinout
SpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . .. 0.5 V to 5.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 50 mA
Package thermal impedance, JA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . .78°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.DescriptionThese 12-bit buffers and line drivers of SN54ABT5402A are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2 ) input is high, all 12 outputs are in the high-impedance state.
The outputs, SN54ABT5402A is designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT5402A is characterized for operation over the full military temperature range of 55°C to 125°C.
The SN74ABT5402A is characterized for operation from 40°C to 85°C.
SN54ABT5402A Data Sheet
