SN54ABT543A

Features: The 'ABT543A octal transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA ) and output-enable (OEAB or OEBA ) inputs are provided for each register to permit independent control in either direction of...

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SeekIC No. : 004496349 Detail

SN54ABT543A: Features: The 'ABT543A octal transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA ) and output-enable (OEAB ...

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Part Number:
SN54ABT543A
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Features:

The 'ABT543A octal transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable  (LEAB or LEBA ) and output-enable (OEAB or OEBA ) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEABis low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB  puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using theCEBA, LEBA, and OEBA inputs.

To ensure the high-impedance state during power up or power down,  OE should be tied to VCC through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking capability of the driver.

The SN54ABT543A is characterized for operation over the full military temperature range of 55to 125. The SN74ABT543A is characterized for operation from 40to 85.




Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . ....0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT543A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 mA
                                                                       SN74ABT543A . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, qJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . ..104/W
                                                                          DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81/W
                                                                          NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67/W
                                                                          PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . 120/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
       2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.




Description

The 'ABT543A octal transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA ) and output-enable (OEAB or OEBA ) inputs of SN54ABT543A are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEABis low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using theCEBA, LEBA, and OEBA inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor SN54ABT543A is determined by the current-sinking capability of the driver.

The SN54ABT543A is characterized for operation over the full military temperature range of 55to 125. The SN74ABT543A is characterized for operation from 40to 85.




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