Features: State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP (Output Ground B...
SN54ABT573: Features: State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p...
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Features: PinoutSpecificationsDescriptionThe SN54/74LS147 and SN54/74LS148 are Priority Encoders. ...
PinoutDescriptionThe LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address in...
State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
High-Drive Outputs (32-mA IOH, 64-mA IOL)
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (N) and Ceramic (J) DIPs

These 8-bit latches feature 3-state outputs of SN54ABT573 designed specifically for driving highly capacitive or relatively low-impedance loads. SN54ABT573 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the SN54ABT573 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input of SN54ABT573 can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive of SN54ABT573 provide the capability to drive bus lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data of SN54ABT573 can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT573 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT573 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT573 is characterized for operation from 40°C to 85°C.