Features: State-of-the-Art EPIC-BTM BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
High-Drive Outputs (32-mA IOH,64-mA IOL)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
SpecificationsSupply voltage range, VCC................................................................................................. 0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1).................................................... 0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO................. 0.5 V to 5.5V
Current into any output in the low state, IO:SN54ABT646............................................................ 96 mA
SN74ABT646............................................................128 mA
Input clamp current, IIK (VI < 0) .................................................................................................. 18 mA
Output clamp current, IOK (VO < 0) ............................................................................................. 50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DB package............................0.65 W
DW package.............................1.7 W
NT package...............................1.3 W
PW package..............................0.7 W
Storage temperature range............................................................................................... 65 to150
DescriptionSN54ABT646 consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions thatcan be performed with the ABT646.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both.
The select-control (SAB and SBA) inputs of SN54ABT646 can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function of SN54ABT646 is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor SN54ABT646 is determined by the current-sinking capability of the driver.
The SN74ABT646 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT646 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT646 is characterized for operation from 40°C to 85°C.
SN54ABT646 Data Sheet
