SN54ABT7820

Features:

􀀀 Member of the Texas Instruments WidebusE Family
􀀀 Advanced BiCMOS Technology
􀀀 Released as DSCC SMD (Standard Microcircuit Drawing) 5962-9650901QXA
􀀀 Independent Asynchronous Inputs and Outputs
􀀀 Two Separate 512 × 18 FIFOs Buffering Data in Opposite Directions
􀀀 Programmable Almost-Full/Almost-Empty Flag
􀀀 Empty, Full, and Half-Full Flags
􀀀 Fast Access Times of 12 ns With a 50-pF Load and Simultaneous Switching Data Outputs
􀀀 Packaged in 84-Pin Ceramic Pin Grid Array


Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . .0.5 V to V_CC + 0.5 V
Voltage range applied to any output in the high state or power-off state, V_O . . . . . . . . . . . . . .0.5 V to 5.5 V
Current into any output in the low state, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 mA
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.


Description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN54ABT7820 is arranged as two 512 * 18-bit FIFOs for high speed and fast access times. SN54ABT7820 processes data at rates up to 40 MHz, with access times of 18 ns in a bit-parallel format.

The SN54ABT7820 consists of bus transceiver circuits, two 512 * 18 FIFOs, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs GAB and GBA control the transceiver functions. The SAB and SBA control inputs select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight fundamental bus-management functions that can be performed with the SN54ABT7820.

The SN54ABT7820 is characterized for operation over the full military temperature range of 55°C to 125°C.