SN54ABT841

Features:

State-of-the-Art EPIC-B^tm BiCMOS Design Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V at V_CC = 5 V, TA = 25°C
High-Impedance State During Power Up and Power Down
High-Drive Outputs (32-mA IOH, 64-mA IOL)
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs


Pinout




Specifications

Supply voltage range, VCC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO  . . . . .. . . . . . . . .  . . . . . .  . .0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT841  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT841A  . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . .   . . . .  . . .  . . . . .  . . . . . . . . . . .  . .  . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current, IOK (VO < 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): DB package   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
DW package   . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . .  . . . . . . . . .  . . . . . . .  . . . . . . . . .  . . . . . . .  . . . . . . . . . 81°C/W
NT package   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   . . . . . . . . . . .   . . .  . . . . . .  . . . . . . . . . . . . . .   . . 67°C/W
PW package   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .  . . . . . . . . . . . . . . . . .   . . . . . . .  .  .  . . .  . . . . . . .120°C/W
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 65°C to 150°C


Description

The SN54ABT841 and SN74ABT841A 10-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. SN54ABT841 and SN74ABT841A are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.The ten transparent D-type latches provide true data at their outputs.

When VCC is between 0 and 2.1 V, the SN54ABT841 and SN74ABT841A are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT841 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT841A is characterized for operation from 40°C to 85°C.