SN54ACT3632

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 0.5 V to V_CC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . ±50 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . ±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . ±400 mA
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. SN54ACT3632 supports clock frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 * 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO SN54ACT3632 has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFO SN54ACT3632 via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths.

The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The SN54ACT3632 enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO SN54ACT3632 are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag of a FIFO SN54ACT3632 are two-stage synchronized to the port clock that reads data from its array. Offset values for the almost-full and almost-empty flags of both FIFOs can be programmed from port A.

The SN54ACT3632 is characterized for operation over the full military temperature range of 55°C to 125°C.

For more information on SN54ACT3632 family, see the following application reports:
` FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007)
` Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors (literature number SCAA005)
` Metastability Performance of Clocked FIFOs (literature number SCZA004)