Pinout
SpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, qJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.DescriptionThe SN54HC32 is a kind of quaruple 2-input positive-OR gate.
Features of of the SN54HC32 are:(1)EPIC (enhanced-performance implanted CMOS) process; (2)operating range 2-V to 5.5-V VCC; (3)latch-up performance exceeds 250 mA per JESD 17; (4)package options include plastic small-outline (DW), shrink small-outline (DB), thin very small-outline (DGV), thin; shrink small-outline (PW), and ceramic flat (W) packages, ceramic chip carriers (FK), and standard plastic (N) and ceramic (J) DIPs.
The absolute maximum ratings of the SN54HC32 can be summarized as:(1): supply-voltage(Vcc) is -0.5 V to 7 V; (2):input clamp current, IIK(Vi<0 V) is -20 mA; (3): output voltage range, Vo is -0.5 V to vcc+0.5 V; (4): continous output current, IO(Vo is 0 to Vcc) is ±25 mA; (5): storage temperature(Tstg) is -65 to +150.
The 'AHC32 devices are quadruple 2-input positive-OR gates. These devices perform the Boolean function Y=A • B or Y= A+B in positive logic. The SN54AHC32 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AHC32 is characterized for operation from 40°C to 85°C.
SN54AHC32 Data Sheet
