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SN54AHCT138

Features: Inputs Are TTL-Voltage Compatible Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Bo...

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SN54AHCT138: Features: Inputs Are TTL-Voltage Compatible Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems Incorporate Three Enable Inputs to Simplify Cascading and/or Data Recep...

SN54AHCT138 Data Sheet

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Part Number:
SN54AHCT138
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Inputs Are TTL-Voltage Compatible
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
    2000-V Human-Body Model (A114-A)
    200-V Machine Model (A115-A)
    1000-V Charged-Device Model (C101)


Application

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Wireless                           www.ti.com/wireless 


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1). . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . .. . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) .. . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC)  . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND .. . . . . . . . . . . . . . . . . . . ±75 mA
Package thermal impedance, JA (see Note 2): D package  . . . . . 73°C/W
                                                     (see Note 2): DB package .. . . . 82°C/W
                                                     (see Note 2): DGV package . .  120°C/W
                                                     (see Note 2): N package . . . . . . 67°C/W
                                                     (see Note 2): NS package . . . . . 64°C/W
                                                     (see Note 2): PW package. . . . 108°C/W
                                                     (see Note 3): RGY package .. . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . 65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
             2. The package thermal impedance is calculated in accordance with JESD 51-7.
             3. The package thermal impedance is calculated in accordance with JESD 51-5.


Description

The SN54AHCT138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, SN54AHCT138 can be used to minimize the effects of system decoding.When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs and the three enable inputs of SN54AHCT138 select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.A 24-line decoder SN54AHCT138 can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.




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