SN54AHCT595

`􀀀 EPICE (Enhanced-Performance Implanted CMOS) Process
`􀀀 Inputs Are TTL-Voltage Compatible
`􀀀 8-Bit Serial-In, Parallel-Out Shift
`􀀀 Shift Register Has Direct Clear
`􀀀 Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
`􀀀 ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
`􀀀 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . .  . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . .  . . . . 0.5 V to 7 V
Output voltage range, V_O (see Note 1) . . . . . . 0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) . . . . . . . . . . ±20 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . ±25 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . .. . . ±50 mA
Package thermal impedance, _JA (see Note 2): D package . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . .. 65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.

The SN54AHCT595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for the shift and storage registers. The shift register SN54AHCT595 has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

Both the shift register clock (RCLK) and storage register clock (SRCLK) are positive-edge triggered. If both clocks are connected together, the shift register SN54AHCT595 always is one clock pulse ahead of the storage register.

The SN54AHCT595 is characterized for operation over the full military temperature range of 55°C to 125°C.

The SN74AHCT595 is characterized for operation from 40°C to 85°C.