SN54ALS163B

Supply voltage range, V_CC . . . . . . . . . . . . . . .-0.5 V to 7V
Input voltage range, V_I  . . . . . . . . . . . . . .. . . -0.5 V to 7V
Package thermal impedance, _JA 
(see Note 1):D package . . . . . . . . .  .   . . . . . . . . .73/W
DB package  . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .82/W
N package . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 67/W
Storage temperature range, T_stg . . . . . . . -60 to 150

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratis only, and functional operation of the device at these or any other conditions beyond those indicated under !recommended operating conditons' is no implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1:The package thermal impedance is calculated in accordance with JESD 51.

These synchronous, presettable, 4-bit decade and binary counters of SN54ALS163B feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The !flALS161B, !flALS163 !flAS161, and !flAS163 devices are 4-bit bina counters. Synchronous operation of SN54ALS163B is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation of SN54ALS163B eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.

These counters are fully programmable; SN54ALS163B can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function of SN54ALS163B for the !flALS161B and 'AS161 devices is asynchronous. A low level at the clear (CLR) input , or enable inputs. The clear sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD function for the SN54ALS162B, !flALS163B, and !flAS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR  to synchronously clear the counter to 0000 (LLLL).

The carry look-ahead circuitry of SN54ALS163B provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output of SN54ALS163B are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled