SN54AS373

Supply voltage, VCC . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . ...7 V
Voltage applied to any output in the high state
or power-off state . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, JA (see Note 1):
DW package . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . .69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . .60°C/W
Storage temperature range, Tstg . . .65°C to 150°C

These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. SN54AS373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs of SN54AS373 are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input of SN54AS373 can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs of SN54AS373 neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the latches. Old data of SN54AS373 can be retained or new data can be entered while the outputs are off.