SN54AS885

These advanced Schottky devices SN54AS885 are capable ofperforming high-speed arithmetic or logiccomparisons on two 8-bit binary or two'scomplement words. Two fully decoded decisionsabout words P and Q are externally available attwo outputs. SN54AS885 is fully expandableto any number of bits without external gates. Tocompare words of longer lengths, the P > QOUTand P < QOUT outputs of a stage handling lesssignificant bits of SN54AS885 can be connected to the P > QINand P < QIN inputs of the next stage handlingmore significant bits. The cascading paths areimplemented with only a two-gate-level delay toreduce overall comparison times for long words.

Two alternative methods of cascading are shownin application information.

The latch is transparent when P latch-enable(PLE) input is high; the P-input port is latchedwhen PLE is low. SN54AS885 provides the designer with temporary storage for the P-data word. The enable circuitryis implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE,P, and Q data inputs utilize pnp input transistors of SN54AS885 to reduce the low-level current input requirement to typically0.25 mA, which minimizes dc loadingeffects.