SN54BCT29826

• State-of-the-Art BiCMOS Design Significantly Reduces I_CCZ
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• 3-State Inverting Buffer-Type Outputs Drive Bus Lines Directly
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT)

These 8-bit bus-interface flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. SN54BCT29826 is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The eight flip-flops of SN54BCT29826 are edge-triggered D-type flip-flops. With the clock-enable (CLKEN) input low, the SN54BCT29826 enters data on the low-to-high transition of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the eight Q outputs to go low independently of the clock.

Buffered output-enable (OE1, OE2, or OE3) inputs of SN54BCT29826 can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable inputs of SN54BCT29826 do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54BCT29826 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74BCT29825 is characterized for operation from 0°C to 70°C.