SN54BCT373

Pinout




Specifications

Supply voltage range, V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to 7 V
Input voltage range, V_I(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, V_O. . . . . . . 0.5 V to 5.5 V
Voltage range applied to any output in the high state, V_O. .. . . . . . . . . . . . . . . . . . . .  0.5 V to V_CC
Input clamp current, I_IK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30 mA
Current into any output in the low state: SN54BCT373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  96 mA
                                                                 SN74BCT373  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 mA
Package thermal impedance, JA (see Note 2): DB package  . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
                                                                          DW package . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
                                                                          N package. . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
                                                                          NS package..... . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150 

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.


Description

These 8-bit latches feature 3-state outputs of SN54BCT373 designed specifically for driving highly capacitive or relatively low-impedance loads. SN54BCT373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.


The eight latches of the SN54BCT373 is transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs.


A buffered output-enable ( OE) input of SN54BCT373 can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs of SN54BCT373 neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.


To ensure the high-impedance state during power up or power down,OECC  through a pullup resistor; the minimum value of the resistor SN54BCT373 is determined by the current-sinking capability of the driver.


OE does not affect the internal operations of the latches. Old data of SN54BCT373 can be retained or new data can be entered while the outputs are in the high-impedance state.