SN54CDC586

Pinout




Specifications

Supply voltage range, VCC   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 0.5 V to 7 V 
Voltage range applied to any output in the high or power-off state,
VO (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   0.5 V to VCC + 0.5 V
Current into any output in the low state, IO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 mA
Input clamp current, IIK (VI < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .65°C to 150°C


Description

The SN54CDC586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz, or down to 25 MHz on outputs configured as half-frequency outputs. The SN54CDC586 operates at 3.3-V VCC and is designed to drive a properly terminated 50-
transmission line. 

The feedback input (FBIN)of SN54CDC586 is used to synchronize the output clocks in frequency and phase to CLKIN. One of the 12 output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input and the outputs. The output of SN54CDC586 used as the feedback pin is synchronized to the same frequency as the CLKIN input.

The Y outputs of SN54CDC586 can be configured to switch in phase and at the same frequency as CLKIN. Select inputs (SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output-signal duty cycles of SN54CDC586 are adjusted to 50%, independent of the duty cycle at CLKIN.