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SN54GTL16612

Features: * Members of Texas Instruments WidebusTM Family* UBT(TM) Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes* OEC(TM) Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference* Translate Betwe...

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SeekIC No. : 004496815 Detail

SN54GTL16612: Features: * Members of Texas Instruments WidebusTM Family* UBT(TM) Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes* O...

SN54GTL16612 Data Sheet

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Part Number:
SN54GTL16612
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

* Members of Texas Instruments WidebusTM Family
* UBT(TM) Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes
* OEC(TM) Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
* Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels
* Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs
* Identical to '16601 Function
* Ioff Supports Partial-Power-Down Mode Operation
* Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port
* Distributed VCC and GND Pins Minimize High-Speed Switching Noise
* Latch-Up Performance Exceeds 500 mA Per JESD 17


Application

Audio
Automotive
Broadband
Digital Control
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless


Pinout

Connection Diagram


Specifications

  MIN              MAX UNIT
VCC Supply voltage range 3.3 V -0.5            4.6 V
5 V -0.5              7
VI Input voltage range(2) A-port and control inputs -0.5              7 V
B port and VREF
 -0.5              4.6
VO Voltage range applied to any output in the high or power-off state(2) A port -0.5               7 V
B port -0.5               4.6
IO Current into any output in the low state A port                       128 mA
B port                         80
IO Current into any A-port output in the high state(3)                         64 mA
  Continuous current through each VCC or GND
                    ±100 mA
IIK Input clamp current VI < 0
                       -50 mA
IOK Output clamp current VO < 0
                       -50 mA
JA
Package thermal impedance(4)		 DGG package                        64 /W
DL package                         56
Tstg Storage temperature range -65                150  



Description

The SN54GTL16612 devices are 18-bit UBTTM  transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The SN54GTL16612 provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC(TM) circuitry.

The user has the flexibility of using SN54GTL16612 at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferredhigher noise margin GTL+ (VTT= 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. V is the reference input voltage for the B port.

VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers.
 




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