SN54GTL16622A

Pinout




Specifications

Supply voltage range, V_CC   . . . . . . . . . . . . . . . . . .  . . . . . . . . . .  . 0.5 V to 4.6 V
Input voltage range, V_I  (see Note 1): A-port and control inputs  . . 0.5 V to 6.5 V
                                                             B port and V_REF   .. . . . . . . . 0.5 V to 4.6 V
Voltage range applied to any output in the high or power-off state,
V_O(see Note 1): A port  . .  . . . . . . . . .. . . . . . ... . . . . . . . . . . . . . .  . 0.5 V to 6.5 V
                         B port  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Current into any output in the low state, I_O : A port   . . . . .  . . . . . . . .  . . . .  48 mA
                                                                        B port  . . . . . . . . . . . . . . . . . .  100 mA
Current into any A-port output in the high state, I_O  (see Note 2) . . . . . . . .. .  48 mA
Continuous current through each V_CC  or GND  . . . . . . . . . . . . . . . . . .. . . .  ±100 mA
Input clamp current, I_IK  (V_I< 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, I_OK  (V_O  < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
 Package thermal impedance, q JA (see Note 3)  . . . . . . . .. . . . . . . . . . . . . .  55°C/W
Storage temperature range, T_stg  65. . . . . . . . . . . . . . . . . . .  . . . . . . .-65  to 150 


Description

     The SN54GTL16622A devices are 18-bit registered bus transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They are partitioned as two separate 9-bit transceivers with individual clock-enable controls and contain D-type flip-flops for  temporary storage of data flowing in either direction. The SN54GTL16622A provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher speed operation of SN54GTL16622A is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and output edge control (OEC(TM)).
     The user has the flexibility of using SN54GTL16622A at either GTL (V_TT= 1.2 V and V_REF = 0.8 V) or the preferred higher noise margin GTL (V_TT  = 1.5 V and V_REF= 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-Vtolerant. V_REF is the reference input voltage for the B port.