SN54HC165

Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-A Max _ICC
Typical t_pd  = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 A Max
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion

The 'HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (Q_H output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabledby a low level at the shift/load (SH/LD) input. The 'HC165 devices also feature a clock-inhibit (CLK INH) functionand a complementary serial (Q_H ) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLKINH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-hightransition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLKis high. Parallel loading is inhibited when SH/LDis held high. While SH/LD is low, the parallel inputs of 'HC165 to theregister are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.