SN54HC166

Synchronous Load
Direct Overriding Clear
Parallel-to-Serial Conversion
Package Options Include Plastic
   Small-Outline (D) and Ceramic Flat (W)
   Packages, Ceramic Chip Carriers (FK), and
   Standard Plastic (N) and Ceramic (J)
   300-mil DIPs

The SN54HC166 parallel-in or serial-in, serial-outregisters feature gated clock (CLK, CLK INH)inputs and an overriding clear (CLR ) input. Theparallel-in or serial-in modes are established bythe shift/load (SH/LD ) input. When high, SH/LD enables the serial (SER) data input and couplesthe eight flip-flops for serial shifting with eachclock (CLK) pulse. When low, the parallel(broadside) data inputs of SN54HC166 are enabled, andsynchronous loading occurs on the next clockpulse. During parallel loading, serial data flow isinhibited. Clocking is accomplished on thelow-to-high-level edge of CLK through a 2-inputpositive-NOR gate permitting one input to be usedas a clock-enable or clock-inhibit function. Holdingeither CLK or CLK INH high inhibits clocking;holding either low enables the other clock input.SN54HC166 allows the system clock to be free running,and the register can be stopped on command withthe other clock input. CLK INH should be changedto the high level only when CLK is high. CLRoverrides all other inputs, including CLK, andresets all flip-flops to zero.

The SN54HC166 is characterized for operation over the full military temperature range of 55 to 125. The SN74HC166 is characterized for operation from 40 to 85.