SN54HC563

Features:

High-Current 3-State Outputs Drive
Bus Lines Directly or up to 15 LSTTL Loads Bus-Structured Pinout
Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs


Pinout




Specifications

Ambient temperature under bias...............................................................-55°C to +125°C
Storage temperature................................................................................ -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)...-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2).................................................0V to +13.25V
Voltage on RA4 with respect to VSS......................................................................0V to +8.5V
Total power dissipation (Note 1) ....................................................................................1.0W
Maximum current out of VSS pin...................................................................................300 mA
Maximum current into VDD pin......................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD).........................................................±20 mA
Maximum output current sunk by any I/O pin..................................................................25 mA
Maximum output current sourced by any I/O pin.............................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)...................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............200 mA
Maximum current sunk by PORTC and PORTD(Note 3) (combined).................................200 mA
Maximum current sourced by PORTC and PORTD(Note 3)(combined).............................200 mA


Description

These 8-bit transparent D-type latches SN54HC563 feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance oads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input of SN54HC563 is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the outputs are latched at the inverses of the levels set up at the D inputs.

A buffered output-enable (OE) input of SN54HC563 places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs of SN54HC563 neither load nor drive the bus lines significantly. The high-impedance state and increased high logic evel provide the capability to drive bus lines without interface or pullup components.