SN54LS193

Features: • Low Power . . . 95 mW Typical Dissipation• High Speed . . . 40 MHz Typical Count Frequency• Synchronous Counting• Asynchronous Master Reset and Parallel Load• Individual Preset Inputs• Cascading Circuitry Internally Provided• Input Clamp Diodes...

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SN54LS193 Picture
SeekIC No. : 004496977 Detail

SN54LS193: Features: • Low Power . . . 95 mW Typical Dissipation• High Speed . . . 40 MHz Typical Count Frequency• Synchronous Counting• Asynchronous Master Reset and Parallel Load̶...

floor Price/Ceiling Price

Part Number:
SN54LS193
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Features:

• Low Power . . . 95 mW Typical Dissipation
• High Speed . . . 40 MHz Typical Count Frequency
• Synchronous Counting
• Asynchronous Master Reset and Parallel Load
• Individual Preset Inputs
• Cascading Circuitry Internally Provided
• Input Clamp Diodes Limit High Speed Termination Effects



Pinout

  Connection Diagram


Specifications

Symbol Parameter   Min Typ Max Unit
VCC Supply Voltage 54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA Operating Ambient Temperature Range 54
74
55
0
25
25
125
70
°C
IOH Output Current - High 54, 74     0.4 mA
IOL Output Current - Low 54
74
    4.0
8.0
mA



Description

The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs.

Separate Terminal Count Up and Terminal Count Down outputs of SN54/74LS192 are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits of SN54/74LS192 to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.




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