SN54LS195A

The Logic Diagram and Truth Table indicate the functionalcharacteristics of the LS195A 4-Bit Shift Register. The deviceis useful in a wide variety of shifting, counting and storageapplications. It performs serial, parallel, serial to parallel, orparallel to serial data transfers at very high speeds.

The LS195A has two primary modes of operation, shift right(Q0  º  Q1) and parallel load which are controlled by the state ofthe Parallel Enable (PE) input. When the PE input is HIGH,serial data enters the first flip-flop Q0 via the J and K inputs andis shifted one bit in the direction Q0  º  Q1  º  Q2  º  Q3 followingeach LOW to HIGH clock transition. The JK inputs provide theflexibility of the JK type input for special applications, and thesimple D type input forgeneral applications by tying the twopins together. When the PE input is LOW, the LS195A appearsas four common clocked D flip-flops. The data on the parallelinputs P0, P1, P2, P3 is transferred to the respective Q0, Q1,Q2, Q3 outputs following the LOW to HIGH clock transition.

Shift left operations (Q3  º  Q2) can be achieved by tying the QnOutputs to the Pn1 inputs and holding the PE input LOW.All serial and parallel datatransfers are synchronous,occurring after each LOW to HIGH clock transition. Since theLS195A utilizes edge-triggering, there is no restriction on theactivity of the J, K, Pn and PE inputs for logic operation -except for the set-up and release time requirements.

A LOW on the asynchronous Master Reset (MR) input setsall Q outputs LOW, independent of any other input condition.