SN54LV132A

Features:

 2-V to 5.5-V V_CC Operation
 Max t_pd of 9 ns at 5 V
 Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
 Typical V_OHV (Output VOH Undershoot) >2.3 V at V_CC = 3.3 V, T_A = 25°C
 Support Mixed-Mode Voltage Operation on All Ports
 Latch-Up Performance Exceeds 250 mA Per JESD 17
 ESD Protection Exceeds JESD 22
    − 2000-V Human-Body Model (A114-A)
    − 200-V Machine Model (A115-A)
    − 1000-V Charged-Device Model (C101)


Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−20 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −50 mA
Continuous output current, I_O (V_O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±50 mA
Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . .  86°C/W
                                                                          DB package . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
                                                                          DGV package . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
                                                                          NS package . . . . . . . . . . . . . . . . . . . . . . . . . .76°C/W
                                                                          PW package . . . . . . . . . . . . . . . . . . . . . . .  113°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. −65°C to 150°C
Voltage range applied to any output in the high-impedance or power-off state, V_O (see Note 1). . . . . .. −0.5 V to 7 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
             2. This value is limited to 5.5 V maximum.
             3. The package thermal impedance is calculated in accordance with JESD 51-7.

Description

The 'LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V V_CC operation.

The 'LV132A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Each circuit functions of LV132A as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals.

These circuits of LV132A are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.