SN54LV138A

`    2-V to 5.5-V V<sub>CC</sub> Operation
`    Max tpd of 9.5 ns at 5 V
`    Typical V<sub>OLP</sub> (Output Ground Bounce)<0.8 V at V<sub>CC</sub> = 3.3 V, T<sub>A</sub> = 25°C
`    Typical V_OHV (Output VOH Undershoot)>2.3 V at V_CC = 3.3 V, T_A = 25°C
`    Support Mixed-Mode Voltage Operation on All Ports
`    I_off Supports Partial-Power-Down Mode Operation
`    Latch-Up Performance Exceeds 250 mA Per JESD 17
`    ESD Protection Exceeds JESD 22
   2000-V Human-Body Model (A114-A)
   200-V Machine Model (A115-A)
   1000-V Charged-Device Model (C101)

SN54LV138A is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory SN54LV138A usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder SN54LV138A can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input of SN54LV138A can be used as a data input for demultiplexing applications.

SN54LV138A is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.