SN54LV374A

Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to 7 V
Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V
Voltage range applied to any output in the high-impedance
  or power-off state, V_O(see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V
Output voltage range applied in the high or low state, V_O(see Notes 1 and 2)  . . . . . 
                                                          . . . . . . . . . . . . . . . . . . . . .-0.5 V to V_CC+ 0.5 V 
Input clamp current, I_IK (V_I< 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20 mA
Output clamp current, I_OK(V_O < 0)   . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .-50 mA
Continuous output current, I_O(V_O = 0 to V_CC)  . . . . . . . . . . . . . . . . . .. . . . . .±35 mA
Continuous current through V_CC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±70 mA
Package thermal impedance, JA(see Note 3): DB package  . . . . . . . . . . . . .  70/W
                                                   (see Note 3): DGV package  . . . . . .. . . . . . .  92/W
                                                   (see Note 3): DW package  . . . . . .  . . . . . . .  58/W
                                                   (see Note 3): GQN package  . . . . .  . . . . . . .  78/W
                                                   (see Note 3): NS package  . . . . . . . . . . . . . .  60/W
                                                   (see Note 3): PW package  . . . . .. . . . . . . . .  83/W
                                                   (see Note 4): RGY package  . . . . . . . . .. . . . .  37/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .-65 to 150


Description

The 'LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V V_CC  operation.

LV374A feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs of LV374A are set to the logic levels set up at the data (D)inputs.