SN54LV4066A

EPIC^TM(Enhanced-Performance ImplantedCMOS) Process
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
Extremely Low Input Current
ESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)
Package Options Include PlasticSmall-Outline (D, NS), Shrink Small-Outline(DB), Thin Very Small-Outline (DGV), ThinShrink Small-Outline (PW), Ceramic Flat(W) Packages, and Standard Plastic (N) andCeramic (J) DIPs

Supply voltage range, V_CC(see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to 7 V
Input voltage range, V_I(see Note 1)  . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .  0.5 V to 7 V
Switch I/O voltage range, V_IO(see Note 1 and 2)  . . . . . . . . . . . . . . . . . . . . 0.5 V to V_CC+ 0.5 V
Control-input clamp current, I_IK(V_I< 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
I/O diode current, I_IOK (V_IO< 0 or V_IO > V_CC)  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .  ±50 mA
On-state switch current, I_T (V_IO = 0 to V_CC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±25 mA
Continuous current through V_CC or GND  . . . . . . . . . . . . .. . . . . . . . . . . . .  . . . . . . . . . . . . .±50 mA
Package thermal impedance, _JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . 127/W
                                                                          DB package . . . . . . . . . . . . . . . . . . . . . . . . 158/W
                                                                          DGV package . . . . . . . . . . . . . . . . . . . . . . . 182/W
                                                                          N package . . . . . . . . . . . . . . . . . . . . . . . . . . 78/W
                                                                          NS package . . . . . . . . . . . . . . . . . . . . . . . . 127/W
                                                                          PW package . . . . . . . . . . . . .  . . . . . . . . . . 170/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150

This quadruple silicon-gate CMOS SN54LV4066A analog switch is designed for 2-V to 5.5-V V_CC operation.

These switches of SN54LV4066A are designed to handle both analog and digital signals. Each switch permits signals withamplitudes up to 5.5 V (peak) to be transmitted in either direction.

Each switch section SN54LV4066A has its own enable-input control (C). A high-level voltage applied to C turns on theassociated switch section.

Applications of SN54LV4066A include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing foranalog-to-digital and digital-to-analog conversion systems.

The SN54LV4066A is characterized for operation over the full military temperature range of 55 to 125.The SN74LV4066A is characterized for operation from 40 to 85.