SN54LVC74A

Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to 6.5 V
Input voltage range, V_I (see Note 1 )  . . . . . . . . . . . . . . . . . . . . . . . . .  -0.5 V to 6.5 V
Output-voltage range, V_O(see Notes 1 and 2)  . . . . . . . . . . . . . . -0.5 V to V_CC+ 0.5 V 
Input clamp current, I_IK (V_I< 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-50mA
Output clamp current, I_OK(V_O < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .-50 mA
Continuous output current, I_O(V_O = 0 to V_CC)    . . . . . . . . . . . . . . . . . .. . . . . .±50 mA
Continuous current through V_CC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±100 mA
Package thermal impedance, JA(see Note 3):  D package. .. . . . . . . . . . . . .  127/W
                                                                          DB package. .. . . . . .. . . . . . .  158/W
                                                                          PW package  . . . . . . . . . . . . . 170/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .-65 to 150


Description

The SN54LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V_CC operation and the SN74LVC74A dual positive- edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

A low level at the preset (PRE) or clear (CLR) inputs of SN54LVC74A sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements of SN54LVC74A is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.