Features: • Members of the Texas Instruments SCOPETM Family of Testability Products
• Members of the Texas Instruments WidebusTM Family
• State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Support Unregulated Battery Operation Down to 2.7 V
• Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data
• Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
• B-Port Outputs of SN74LVT182502 Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPETM Instruction Set
IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
Parallel Signature Analysis at Inputs
Pseudo-Random Pattern Generation From Outputs
Sample Inputs/Toggle Outputs
Binary Count From Outputs
Device Identification
Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings
Pinout
SpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO (see Note 1) . . . .0.5 V to 7 V
Current into any output in the low state, IO: SN54LVTH18652A . . . . . . . . . . . . . . . . . . . . . . . . . .96 mA
SN54LVTH182652A (A port or TDO) . . . . . . . . . . .. .96 mA
SN54LVTH182652A (B port) . . . . . . . . . . . . . . . . . . .30 mA
SN74LVTH18652A . . . . . . . . . . . . . . . . . . . . . . . . .128 mA
SN74LVTH182652A (A port or TDO) . . . . . . . . . . ..128 mA
SN74LVTH182652A (B port) . . . . . . . . . . . . . . . . . . .30 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH18652A . . . . . . . . . . . . .. . .48 mA
SN54LVTH182652A (A port or TDO) . .48 mA
SN54LVTH182652A (B port) . . . . . . .. .30 mA
SN74LVTH18652A . . . . . . . . . . . . . . . .64 mA
SN74LVTH182652A (A port or TDO) . . .64 mA
SN74LVTH182652A (B port) . . . . . . . . .30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .50 mA
Package thermal impedance,JA (see Note 3): PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .65°C to 150°CDescriptionThe SN54LVTH18652A and SN54LVTH182652Ascan test devices with 18-bit bus transceivers and registers are members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry of SN54LVTH18652A and SN54LVTH182652A is accomplished via the 4-wire test access port (TAP) interface.
Additionally, SN54LVTH18652A and SN54LVTH182652A are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
In the normal mode, SN54LVTH18652A and SN54LVTH182652A are 18-bit bus transceivers and registers that allow for multiplexed transmission of data directly from the input bus or from the internal registers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry of SN54LVTH18652A and SN54LVTH182652A can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers and registers.
Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and output-enable (OEAB and OEBA) inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers SN54LVTH18652A and SN54LVTH182652A on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). When OEAB is high, the B outputs of SN54LVTH18652A and SN54LVTH182652A are active. When OEAB is low, the B outputs are in the high-impedance state.
Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and OEBA inputs. Since the OEBA input is active-low, the A outputs are active when OEBA is low and are in the high-impedance state when OEBA is high. Figure 1 illustrates the four fundamental bus-management functions SN54LVTH18652A and SN54LVTH182652A can be performed with the 'LVTH18652A and 'LVTH182652A.
In the test mode, the normal operation of the SCOPE SN54LVTH18652A and SN54LVTH182652A bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the SN54LVTH18652A and SN54LVTH182652A. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins of SN54LVTH18652A and SN54LVTH182652A are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry of SN54LVTH18652A and SN54LVTH182652A performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry SN54LVTH18652A and SN54LVTH182652A is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs of 'LVTH182652A, which are designed to source or sink up to 12 mA, include equivalent 25-W series resistors to reduce overshoot and undershoot.
The SN54LVTH18652A and SN54LVTH182652A are characterized for operation over the full military temperature range of 55°C to 125°C. The SN74LVTH18652A and SN74LVTH182652A are characterized for operation from 40°C to 85°C.
SN54LVTH18652A Data Sheet
