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SN64BCT657

Features: • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)• High-Impedance State During Power Up and Power Down• 3-State B Outputs Sink 64 mA and S...

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SeekIC No. : 004497313 Detail

SN64BCT657: Features: • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)&...

SN64BCT657 Data Sheet

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Part Number:
SN64BCT657
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Features:

• State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• High-Impedance State During Power Up and Power Down
• 3-State B Outputs Sink 64 mA and Source 15 mA
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . .  . .0.5 V to 5.5 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VCC
Input clamp current, IIK(VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 mA
Current into any output in the low state ,IO . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .   60 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .  -40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. .65°C to 150°C  


Description

The SN64BCT657 contains eight noninverting buffers with parity generator/checker circuits and control signals. The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode). When the output-enable (OE) input is high, both the A and B ports of SN64BCT657 are in the high-impedance state.

Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity bit value; SN64BCT657 is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.

In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY SN64BCT657 is set to the logic level that maintains the parity sense selected by the level at the ODD/EVEN input. For example, if ODD/EVEN is low (even parity selected) and there are five high bits on the A bus, then PARITY SN64BCT657 is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.

In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic level indicates whether or not the data of SN64BCT657 to be received exhibits the correct parity sense. For example, if ODD/EVEN is high (odd parity selected), PARITY SN64BCT657 is high, and there are three high bits on the B bus, then ERR is low, indicating a parity error.

The SN64BCT657 is characterized for operation from 40°C to 85°C and 0°C to 70°C.




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