SN65LVDM320 Selling Leads, Price trend, SN65LVDM320 DataSheet download, circuit diagram from SeekIC.com

Features: ` 8-Bit Bidirectional Data Storage Register With Full Parallel Access` Parallel Transfer Rates† Buffer Mode: Up to 475 Megatransfers Flip-Flop Mode: Up to 300 Megatransfers Latch Mode: Up to 300 Megatransfers` Operates With a Single 3.3-V Supply` Low-Voltage Differential Signali...

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SeekIC No. : 004497444 Detail

SN65LVDM320: Features: ` 8-Bit Bidirectional Data Storage Register With Full Parallel Access` Parallel Transfer Rates† Buffer Mode: Up to 475 Megatransfers Flip-Flop Mode: Up to 300 Megatransfers Latch ...

SN65LVDM320 Data Sheet

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Part Number:: SN65LVDM320
Supply Ability:: 5000

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Upload time: 2025/12/24

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Product Details

Description

Features:

` 8-Bit Bidirectional Data Storage Register With Full Parallel Access
` Parallel Transfer Rates†
    Buffer Mode: Up to 475 Megatransfers
    Flip-Flop Mode: Up to 300 Megatransfers
    Latch Mode: Up to 300 Megatransfers
` Operates With a Single 3.3-V Supply
` Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV Across a 50-Ω Load
` Bus and Logic Loopback Capability
` Very Low Radiation Emission
` Low Skew Performance
    Pulse Skew Less Than 100 ps
     Output Skew Less Than 320 ps
     Part-to-Part Skew Less Than 1 ns
`Open-Circuit Differential Receiver Fail Safe Assures a Low-Level Output
` Reset at Power Up
` 12-kV Bus-Pin ESD Protection
` Bus Pins Remain High-Impedance When Disabled or With VCC Below 1.5 V for Power-Up/Down Glitch-Free Performance and Hot Plugging
` 5-V Tolerant LVCMOS Inputs

Application

· Telecom Switching
· Printers and Copiers
· Audio Mixing Consoles
· Automated Test Equipment

Pinout

Connection Diagram

Specifications

Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4 V
Voltage range:(TTL pins) . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .0.5 V to VCC + 6V
BY and BZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . 0.5 V to 4 V
Electrostatic discharge: Y, Z, and GND(see Note 2) . . . . . . .. . . . Class 3, A: 12 kV, B: 600 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 3, A: 7 kV, B: 500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . .See Dissipation Rating Table
Storage Temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . .260°C
1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883E Method 3015.7.

Description

The SN65LVDM320 is an 8-bit data storage register with differential line drivers and receivers that are electrically compatible with ANSI EIA/TIA-644 for multipoint architectures with standard-compliant parallel transfer rates of 475 Mbps. The SN65LVDM320 includes transmitter and receiver data registers that remain active regardless of the state of their associated outputs.

The logic element for data flow in each direction SN65LVDM320 is configured by mode-control inputs. IMODE1 and IMODE2 control data flow in the B-to-A (bus side to digital side) direction when configured as a buffer, a D-type flip-flop, or a D-type latch. OMODE1 and OMODE2 control data flow in each of the operating modes for the A-to-B (digital side to bus side) direction. When configured in buffer mode, input data appears at the output port. In the flip-flop mode, data of SN65LVDM320 is stored on the rising edge of the appropriate clock input, CLKAB/LEAB or CLKBA/LEBA. In the latch mode, this clock pin of SN65LVDM320 also serves as an active-high transparent latch enable.

Data flow is further controlled by the A-side loopback (LPBK) input. When LPBK is high, DA input data of SN65LVDM320 is looped back to the RA output. B-side bus data is looped back to the bus in latch mode by means of the IMODE and OMODE logic states.

The A-side output enable/disable control of SN65LVDM320 is provided by OEA. When OEA is low or VCC is less than 2 V, the A side is in the high-impedance state. When OEA is high, the A side is active (high or low logic levels). The B-side output enable/disable control is provided by OEB. When OEB is low or VCC is less than 2 V, the B side is in the high impedance state. When OEB is high, the B side is active (high or low logic levels).

The A-to-B and B-to-A logic elements SN65LVDM320 are active regardless of the state of their associated outputs. New data can be entered (in latch and flip-flop modes) or previously stored data can be retained while the associated outputs are in the high-impedance or inactive states. The SN65LVDM320 also includes internally isolated analog (B-side) and digital (A-side) grounds for enhanced operation.

The SN65LVDM320 is characterized for operation from 40°C to 85°C.

SN65LVDM320

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