ApplicationA LVDS receiver can be used to receive various other types of logic signals. Figure 19 through Figure 28 show the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
Pinout
SpecificationsSupply voltage range, VCC(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 4 V
Voltage range, Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .0.5 to 6 V
A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 4 V
Electrostatic discharge (see Note 2); Y, Z, and GND . . . . . . . . . . . . . . . . . . . .Class 3, A:16 kV, B: 600 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B: 500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . .. . . . . .260°CDescriptionThe SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique, SN65LVDS104 and SN65LVDS105 offer low-power, lownoise coupling, and switching speeds to transmit data at speeds up to 655 Mbps at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The intended application of SN65LVDS104 and SN65LVDS105 and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 W. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. SN65LVDS104 and SN65LVDS105 are particularly advantageous in distribution or expansion of signals such as clock or serial data stream.
The SN65LVDS104 and SN65LVDS105 are characterized for operation from 40°C to 85°C.
SN65LVDS104 Data Sheet
