ApplicationAn LVDS receiver can be used to receive various other types of logic signals. Figure 11 through Figure 19 show the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
Pinout
SpecificationsSupply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..0.5 V to 4 V
Input voltage range, Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .0.5 V to 6 V
A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .0.5 V to 4 V
Electrostatic discharge, Y, Z, and GND (see Note 2) : . . . . . . . . . . . . . . . . . . .. .Class 3, A:12 kV, B:500 V
All pins . . . . . . . . . . . . . . . . .. . . . . . . . . . .. .Class 3, A: 4 kV, B:400 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . .. . . . .260°CDescriptionThe SN65LVDS116 is one differential line reciever connected to sixteen differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS,as specified in EIA/TIA-644, SN65LVDS116 is a data signaling technique that offers the low-power, low-noise coupling, and switching speeds to transmit data at speeds up to 622 Mbps and relatively long distances. (Note:The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media,the noise coupling to the environment, and other system characteristics.)
The intended application of SN65LVDS116 and signaling technique is for point-to-point or multidrop baseband data transmission over controlled impedance media of approximately 100 W. The transmission media may be printed circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. SN65LVDS116 is particularly advantageous in system clock distribution.
The SN65LVDS116 is characterised for operation from 40°C to 85°C.
SN65LVDS116 Data Sheet
