SN65LVDS151DA

Maximum Operating Temperature : + 85 C
Operating Supply Voltage : 3.3 V
Packaging : Tube
Number of Drivers : 1
Data Rate : 200 Mbps
Number of Receivers : 10
Maximum Power Dissipation : 1453 mW
Package / Case : TSSOP-32


Description

The SN65LVDS151DA belongs to SN65LVDS151 family which consists of a 10-bit parallel-in/serial-out shift register, three LVDS differential transmission line receivers, a pair of LVDS differential transmission line drivers, plus associated input buffers. SN65LVDS151DA accepts up to 10 bits of user data on parallel data inputs (DI0 DI9) and serializes (multiplexes) the data for transmission over an LVDS transmission line link. The multiplexing ratio M, or number of bits per data clock cycle, is programmed on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier with configuration pins (M1 M5). The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier is between 4 and 40. Two or more SN65LVDS151 units may be connected in series (cascaded) to accommodate wider parallel data paths for higher serialization values. Data is transmitted over the LVDS serial link at M times the input parallel data clock frequency. Cascade input enable (CI_EN) is used to turn off the CI input when it is not being used. Serialized data bits are output from the DO output, starting in ascending order, from parallel input bit DI0. The number of serialized data bits output per data clock cycle is determined by the multiplexing ratio M. For values of M less than or equal to 10, the cascade input (CI±) is not used, and only the first M parallel input bits (DI0 thought DI[M1]) are used. For values of M greater than 10, all ten parallel input bits (DI0 though DI9) are used, and the cascade input is used to shift in the remaining data bits from additional SN65LVDS151 serializers. Table 2 shows which input data bits are used as a function of the multiplier M. The data of SN65LVDS151DA is read out serially from the SN65LVDS151 shift registers on the rising edges of the M-clock input (MCI). The lowest order bit of parallel input data, DI0, is output from DO on the third rising edge of MCI following the rising edge of LCRI. The remaining bits of parallel input data, DI-1 DI-(M-1) are clocked out sequentially, in ascending order, by subsequent MCI rising edges. Data of SN65LVDS151DA is parallel loaded into the SN65LVDS151 input latches on the first rising edge of the M-clock input (MCI) signal following a rising edge of the link clock reference input (LCRI). The link clock output (LCO) signal rising edge is synchronized to the data output (DO) by an internal circuit clocked by MCI. The LCO signal rising edge follows the first rising edge of MCI after the rising edge of LCRI. Examples of operating waveforms for values of M = 4 and M = 10 are provided in Figure 1. Both the LCRI and MCI signals are intended to be sourced from the SN65LVDS150 MuxIt programmable frequency multiplier. They are carried over LVDS differential connections to minimize skew and jitter. The SN65LVDS151 includes LVDS differential line drivers for both the serialized data output (DO) stream and the link clock output (LCO). The cascade input (CI) is also an LVDS connection, and when it is used SN65LVDS151DA is tied to the DO output of the preceding SN65LVDS151. An internal power-on reset (POR) and an enable input (EN) control the operation of the SN65LVDS151. When VCC is below 1.5 V, or when EN is low, the device is in a low-power disabled state, and the DO and LCO differential outputs are in a high-impedance state. When VCC is above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock output of SN65LVDS151DA enable input (LCO_EN) is used to turn off the LCO output when it is not being used.

The features of SN65LVDS151DA can be summarized as (1)a member of the muxit serializer-deserializer building-block chip family; (2)supports serialization of up to 10 bits of parallel data input at rates up to 200 Mbps; (3)PLL lock/valid input provided to enable link data transfers; (4)cascadable with additional SN65LVDS151 muxit serializer-transmitters for wider parallel input data channel widths; (5)LVDS compatible differential inputs and outputs meet or exceed the requirements of ANSI TIA/EIA-644-A; (6)LVDS inputs and outputs ESD Protection exceeds 12 kV HBM; (7)LVTTL compatible inputs for lock/valid, enables, and parallel data inputs are 5-V tolerant; (8)operates with 3.3 V supply; (9)packaged in 32-Pin DA thin shrink small-outline package with 26 mil terminal pitch.

The absolute maximum ratings of SN65LVDS151DA are (1)supply voltage range, VCC (see Note 1): 0.5 V to 4 V; (2)voltage range: DI0 through DI9 input:s 0.5 V to VCC5 +0.5 V, EN, CI_EN, LCO_EN, LVI inputs, VCC5: 0.5 V to 5.5 V, CI±, LCRI±, or MCI± Inputs, DO±, or LCO± outputs: 0.5 to 4 V; (3)Electrostatic discharge, human body model (see Note 2): MCI±, LCRI±, CI±, DO±, LCO±, and GND: ±12 kV, All pins: ±2 kV, charged-device model (see Note 3): all pins ±500 V; (4)continuous power dissipation: see dissipation rating table; (5)storage temperature range: 65°C to 150°C; (6)lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: 260°C.(NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with JEDEC Standard 22, Test Method A114B. 3. Tested in accordance with JEDEC Standard 22, Test Method C101.)