SN65LVDS152

    MuxIt SN65LVDS152 is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher transmission efficiencies than with other existing fixed ratio solutions. MuxIt SN65LVDS152 utilizes the LVDS (TIA/EIA-644-A) low voltage differential signaling technology for communications between the data source and data destination.

    The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152 receiver deserializer.

    The SN65LVDS152 consists of three LVDS differential transmission line receivers, an LVDS differential transmission line driver, a 10-bit serial-in/parallel-out shift register, plus associated input and output buffers. It receives serialized data over an LVDS transmission line link, deserializes (demultiplexes) it, and delivers it on parallel data outputs, DO0 through DO9. Data received over the link is clocked at a factor of M times the original parallel data frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed with configuration pins (M1 M5) on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier. Up to 10 bits of data may be deserialized and output by each SN65LVDS152. Two or more SN65LVDS152 units may be connected in series (cascaded) to accommodate wider parallel data paths for higher serialization values. The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier is between 4 and 40. Table 1 shows some of the combinations of LCI and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.

    Data is serially shifted into the SN65LVDS152 shift register on the falling edges of the M-clock input (MCI). The data is latched out in parallel from the SN65LVDS152 shift register on the second rising edge after the first falling edge of the M-clock following a rising edge of the link clock input (LCI). The SN65LVDS152 includes LVDS differential line receivers for both the serialized link data stream (DI) and link clock (LCI). High-speed signals from the SN65LVDS150 MuxIt programmable frequency multiplier (MCI), plus the input and output for cascaded data (DI, CO) are carried over differential connections to minimize skew and jitter. Examples of operating waveforms for values of M = 4 and M = 10 are provided in Figure 1.

    The SN65LVDS152 enable input (EN) along with internal power-on reset (POR) controls the outputs. When Vcc is below 1.5 volts, or when EN is low, outputs are disabled. When V_CC is above 3 V and EN is high, outputs are enabled and operating to specifications.

    Parallel data bits are output from DOn outputs in an order dependent on the value of the multiplexing SN65LVDS152 ratio (frequency multiplier value) M. For values of M from 4 through 10, the cascade output (CO+/) is not used, and only the top M parallel outputs (DO9 through DO[10M]) are used. The data bit output on DO9 corresponds to the data bit input on DI[M1] of the SN65LVDS151 serializer. Likewise, the data bit output on DO[10M] will correspond to the data bit input on DI0 of the SN65LVDS151 serializer.

    For values of M greater than 10, the cascade output (CO+/) is used to connect multiple SN65LVDS152 deserializers. In this case the higher-order unit(s) output 10 bits each of the highest numbered bits that are input into the SN65LVDS151 serializer(s). The lowest numbered input bits are output on the lowest-order SN65LVDS152 deserializer in descending order from output DO9. The number of bits is equal to M mod(10). Table 2 reflects this information, where X = M mod(10)