SN65LVDS2

One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between 100 mV and 100 mV and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles the open-input circuit situation, however.

Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near V_CC through 300-kW resistors as shown in Figure 10. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage.

It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature.

The SN65LVDS2 is a single low-voltage differential line receiver in a small-outline transistor package. The inputs comply with the TIA/EIA-644 standard and provide a maximum differential input threshold of 100 mV over an input common-mode voltage range of 0 V to 2.4 V.

When SN65LVDS2 is used with a low-voltage differential signaling (LVDS) driver (such as the SN65LVDS1) in a point-to-point or multidrop configuration; data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption.

The high-speed switching of LVDS SN65LVDS2 signals requires the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. TI offers you both the SN65LVDS2, which requires this external resistor, or its companion the SN65LVDT2, which eliminates the need by integrating it with the receiver.The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make SN65LVDS2 ideal for battery-powered applications.

The SN65LVDS2 is characterized for operation from 40°C to 85°C.