SN65LVDS386DGG

The SN65LVDS386DGG belongs to SN65LVDS386 family. SN65LVDS386DGG of four-, eight-, or sixteen-, differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). Any of the eight or sixteen differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. When used with its companion, 8- or 16-channel driver, the SN65LVDS389 or SN65LVDS387, over 300 million data transfers per second in single-edge clocked systems are possible with little power. (Note: The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.). The LVDT products eliminate this external resistor by integrating it with the receiver. The intended application of SN65LVDS386DGG and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers.

The features of SN65LVDS386DGG can be summarized as (1)four- ('390), eight- ('388a), or sixteen- ('386) line receivers meet or exceed the requirements of ANSI TIA/EIA-644 Standard; (2)integrated 110- line termination resistors on LVDT products; (3)designed for signaling rates (1) up to 630 Mbps; (4)SN65 version's bus-terminal ESD exceeds 15 kV; (5)operates from a single 3.3-V supply; (6)typical propagation delay time of 2.6 ns; (7)output skew 100 ps (Typ) part-to-part skew is less than 1 ns; (8)LVTTL levels are 5-V tolerant; (9)open-circuit fail safe; (10)flow-through pinout; (11)packaged in thin shrink small-outline package with 20-mil terminal pitch.

The absolute maximum ratings of SN65LVDS386DGG are (1)VCC (2) supply voltage range: 0.5 V to 4 V; (2)VI voltage range: enables or Y: 0.5 V to 6 V, A or B: 0.5 V to 4 V; (3)IO output current Y: ±12 mA; (4)continuous power dissipation: see dissipation rating table; (5)Tstg storage temperature range: 65°C to 150°C; (6)lead temperature 1,6 mm (1/16 in) from case for 10 seconds: 260°C((1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with MIL-STD-883C Method 3015.7) .