SN65LVDS94

Pinout




Specifications

Supply voltage range, V_CC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . .  . . . .... . . . . . .0.3 V to 4 V
Voltage range at any terminal (except SHTDN) . . . . . . . . . . . . . . . . . . . . . ....0.5 V to VCC + 0.5 V
Voltage range at SHTDN terminal . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 0.5 V to VCC + 3 V
Electrostatic discharge (see Note 2): Bus pins (Class 3A)  . . . .. . . . . . . . . . . . . ... . . . . . . . . .. .4 KV .
                                                           Bus pins (Class 2B)  . . . . . . . . . . . . . . . . . . . . . . .  . . . .200 V
                                                           All pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . ........3 KV
                                                           All pins (Class 2B)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 V
Continuous total power dissipation  . . . . . . . . . . . . . . . . . . . . . . .. . .(see Dissipation Rating Table)
Operating free-air temperature range, T_A  . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .40°C to 85°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds  . . . . . . . . . . . . . . . . . . . . .260°C


Description

The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7* clock synthesizer,and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions of SN65LVDS94 allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data of SN65LVDS94 is received and loaded into registers at the rate seven times the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7* clock for internal clocking and an output clock for the expanded data.The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).

The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control.The data bus appears the same at the input to the transmitter and output of the receiver with the data of SN65LVDS94 transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The SN65LVDS94 is characterized for operation over ambient air temperatures of 40°C to 85°C.