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SN65LVDT250

Features: ` Greater Than 2.0 Gbps Operation` Nonblocking Architecture Allows Each Output to be Connected to Any Input` Pk-Pk Jitter: 60 ps Typical at 2.0 Gbps 110 ps Typical at 2.5 Gbps` Compatible With ANSI TIA/EIA-644-A LVDS Standard` Available Packaging 38-Pin TSSOP` 25 mV of Input Voltage Thre...

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SN65LVDT250: Features: ` Greater Than 2.0 Gbps Operation` Nonblocking Architecture Allows Each Output to be Connected to Any Input` Pk-Pk Jitter: 60 ps Typical at 2.0 Gbps 110 ps Typical at 2.5 Gbps` Compatible ...

SN65LVDT250 Data Sheet

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Part Number:
SN65LVDT250
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` Greater Than 2.0 Gbps Operation
` Nonblocking Architecture Allows Each Output to be Connected to Any Input
` Pk-Pk Jitter:
60 ps Typical at 2.0 Gbps
110 ps Typical at 2.5 Gbps
` Compatible With ANSI TIA/EIA-644-A LVDS Standard
` Available Packaging 38-Pin TSSOP
` 25 mV of Input Voltage Threshold Hysteresis
` Propagation Delay Times: 800 ps Typical
` Inputs Electrically Compatible With LVPECL, CML and LVDS Signal Levels
` Operates From a Single 3.3-V Supply
` Low Power: 110 mA Typical
` Integrated 110-W Line Termination Resistors Available With SN65LVDT250


Application

· Clock Buffering/Clock Muxing
· Wireless Base Stations
· High-Speed Network Routing
· Telecom/Datacom


Pinout

Connection Diagram


Specifications

  UNITS
Supply voltage range, VCC 0.5 V to 4 V
voltage range(2) S, DE 0.5 V to 4 V
A, B 1.8 V to 4 V
|VA - VB| (LVDT only) 1 V
Y, Z -0.5 V to 4 V
Electrostatic discharge Human Body Model(3) All pins ±3 kV
Charged-Device Model(4) All pins ±1500 V
Continuous power dissipation See Dissipation Rating Table


(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.




Description

The SN65LVDS250 and SN65LVDT250 are 4x4 nonblocking crosspoint switches in a flow-through pin-out allowing for ease in PCB layout. Low-voltage differential signaling (LVDS) is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT250 incorporates 110-W termination resistors for those applications where board space is a premium.

The SN65LVDS250 and SN65LVDT250 are characterized for operation from -40°C to 85°C.




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